Communication between integrated circuit systems commonly requires that the phase and/or frequency of an input signal be matched, or “locked” to a local signal, such as a clock signal. A typical system for accomplishing this is the phase-locked loop (PLL).
FIG. 1 is a block diagram of a conventional phase locked loop configuration. The conventional PLL 11 includes a phase frequency detector (PFD) 10, a first charge pump (CP) 12, an operational amplifier 16, and a voltage controlled oscillator (VCO) 18. An optional second charge pump (CP) 14 may also be included.
The phase frequency detector 10 measures a phase difference between a received reference clock signal RCLK and a feedback clock signal VCLK. In response to the difference in phase between the clock signals, the phase frequency detector 10 generates an up control signal up and a down control signal dn, which are provided to the first charge pump 12. The first charge pump 12, in turn, charges and discharges a first capacitor Cp of a loop filter in response to the up control signal up and down control signal dn, in turn generating a loop filter control voltage Vp. The loop filter control voltage Vp is provided to the VCO to determine the output frequency of the VCO 18.
In combination, the first charge pump 12 and first capacitor provide a pole for the feedback loop, however, it is preferred that a loop-stabilizing zero also be included in order to maintain stability in the phase locked loop. A resistor can be placed in series with the first capacitor Cp for this purpose. This embodiment, however, is prone to process and temperature variation, which, in turn, can lead to variable operation characteristics. In addition, the value of the series resistor is difficult to adjust and reproduce accurately.
In an alternative embodiment shown in FIG. 1, a zero for the feedback loop is provided by the combination of the second charge pump 14, the operational amplifier 16, and a second capacitor Cc. The second charge pump 14 receives the up control signal up and down control signal dn, and, in response, charges and discharges the second capacitor Cc. The operational amplifier 16 receives at a positive input terminal the loop filter control voltage Vp, and provides, at an output terminal, a VCO control voltage Vc, that is applied to the second capacitor Cc. A closed-loop negative feedback signal is provided between the output terminal and negative input terminal of the operational amplifier 16. The VCO control voltage Vc is applied to the VCO to determine the output frequency of the VCO 18.
While the configuration of FIG. 1 provides for a relatively stable phase locked loop operation, the current Ip that is provided by the first charge pump 12 is fixed, and therefore, the locking time period for the loop is less than optimal. Also, the second charge pump 14 used in combination with the operational amplifier 16 to improve loop stability requires a large area of the chip die, leading to manufacturing inefficiencies.